Simulasi Gerbang Logika Dengan Menggunakan Aplikasi Zeliosoft 2
DOI:
https://doi.org/10.55606/jtmei.v3i1.3171Keywords:
Logic Gate, Zelio Soft 2, FBD (Function Block Diagrams)Abstract
The background for carrying out this research is to create a logic gate simulation using a PLC (Programmable Logic Controlled) application, namely using the Zeliosoft 2 application, thereby reducing the risk of damage when creating electronic circuits manually. The aim of this research is to show the effectiveness of logic gates and how to operate them using the Zeliosoft 2 program. This research uses a simulation approach with a laptop running the Zelio Soft 2 program in the Electrical Engineering Vocational Education laboratory. The results obtained show that the simulation results carried out on the application are in accordance with the logic gate truth table. This is proven by the data produced in the research on each logic gate which is simulated according to the truth table.
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